IAR Information Center for MSP430

Important information
New features
Known problems
Program corrections
User guide corrections
Miscellaneous
Release history

Important information

When building a pure assembler project from IAR Embedded Workbench, the Exclude RESET vector option should be used. This option has change name from Assembler only project, and will still exclude the runtime library from the project.
When using the macros.m43 file replace the following:

XBR #func XCALL #func

with

XXBR func XXCALL func

The old format is still supported, although deprecated. The reason behind the change is that the old macros do not work with ROPI.
Deprecated features
- --ropi
  The support for position-independent code and read-only data (ROPI) will be removed in future versions of the IAR C/C++ Assembler for MSP430.

New features

None.

See user guide corrections for more information.

Known Problems

[EW430-1501] The compiler does not emit an error message when a public EQU refer to an external symbol.
[EW430-1405, EW10132]
The reference guide, page 6, gives the impression that the character sequence \' and '' both will generate the character ' inside a string. This is not the case in the following example:
```
DB '''ABCD' ; Error[0]: Invalid syntax
```
[EW430-1380, EW11791] If a move of an immediate value to a numeric address in symbolic mode, for example MOV #0x1234, 0x300, is made in a RSEG or ASEG, the offset is calculated as if the code began at address 0x0000. The assembler does not take into account the placement of the segment.
[EW430-970, EW18097]
Crossing an IF block with a half-solved condition or an unsolved condition can give internal errors.

Example:
```
label1:
    IF $-label1
    ENDIF
    call #label1
```
[EW430-551, EW22547] The conditional assembly directives might misinterpret conditional assembly directives inside comments inside the directive.

Program Corrections

None

User guide corrections

The corrections below refer to the PDF version of the user guide MSP430 Assembler Reference Guide, A430-4.

None.

Miscellaneous

Workarounds for hardware problems:
- CPU4:
  
  For the MSP430 architecture (-v0), the assembler uses a safe alternative encoding for PUSH #4/#8 instructions.
- CPU6:
  
  When -h is given, the assembler gives an error for @Rn operands unless Rn is PC. The runtime libraries are built with -h enabled, but the IDE does not automatically enable this workaround for affected devices.
- CPU8:
  
  You must take care never to put an odd value into the SP register. Also, the compiler assumes that the value in the SP register is always even. The assembler files in the runtime library never put odd values into the SP register.
- CPU11, CPU12, CPU13, CPU45:
  
  Not handled by the IAR Embedded Workbench for MSP430 toolchain.
- CPU15:
  
  In situations where a device affected by CPU15 would branch to a different location than an unaffected device, you can add the symbolic value ?CPU15_OFFSET to the branch offset. This value is defined in the linker command files to be either 0 (for unaffected devices), or 2 (for affected devices). The assembler files in the runtime library use ?CPU15_OFFSET where necessary to work with both affected and unaffected devices.
- CPU16:
  
  You must take care to write code that works with the chosen target device. In the runtime library, the assembler files have been written to work with both affected and unaffected devices.
- CPU18, CPU19, CPU24, CPU25, CPU27, CPU29:
  
  If the option --hw_workaround=nop_after_lpm is given to the assembler, it will issue a warning when it detects an instruction that might change the LPM bits in the status register SR, unless it is immediately followed by a NOP. If you are sure that the instruction in question cannot change the LPM bits, you can suppress the warning by placing the assembler directive SUPPRESS_NOP_AFTER_LPM_WARNING on the line just before the line that triggers the warning. The runtime libraries are built with --hw_workaround=nop_after_lpm enabled, and the IDE enables it automatically for all affected devices.
- CPU20:
  
  The linker command files for affected devices do not allow code in default segments to be placed in the last four bytes of a memory region that is not followed by valid memory. If you modify the address ranges in the linker command file, or place code in custom segments, you must ensure that this constraint is still met.
- CPU21:
  
  The instruction POPM #1, SR triggers an error in the assembler.
- CPU22:
  
  @PC operands are not useful in real applications. You must take care not to write @PC operands in assembler code. In the runtime library, the assembler files do not use @PC operands.
- CPU23, CPU34:
  
  Instructions that rotate the PC register are not useful in real applications. You must take care not to write instructions that rotate the PC register in assembler code. In the runtime library, the assembler files never rotate the PC register.
- CPU26:
  
  You must take care not to write CALL SP instructions in assembler code. In the runtime library, the assembler files do not use CALL SP instructions.
- CPU28:
  
  You must take care not to write instruction sequences that trigger this issue. In the runtime library, the assembler files do not use instruction sequences that trigger this issue.
- CPU30:
  
  In situations where a device affected by CPU30 would branch to a different location than an unaffected device, you can add the symbolic value ?CPU30_OFFSET to the branch offset. This value is defined in the linker command files to be either 0 (for unaffected devices), or 2 (for affected devices). The assembler files in the runtime library use ?CPU30_OFFSET where necessary to work with both affected and unaffected devices.
- CPU31:
  
  You must take care not to use auto-increment mode in push instructions in assembler code. In the runtime library, the assembler files do not use auto-increment mode in push instructions.
- CPU32:
  
  You must take care not to write CALLA PC instructions in assembler code. In the runtime library, the assembler files do not use CALLA PC instructions.
- CPU33:
  
  Negative stack offsets are not allowed in real applications, because they would access the unallocated memory outside the current stack. Such memory can be corrupted at any time by interrupts. You must take care not to use negative stack offsets in assembler code. In the runtime library, the assembler files do not use negative stack offsets.
- CPU35:
  
  You must take care not to write BIT.B @Rx, PC instructions in assembler code. In the runtime library, the assembler files do not use BIT.B @Rx, PC instructions.
- CPU39:
  
  For the MSP430X architecture (-v1), the assembler issues a warning if there is no NOP after any instruction that might disable interrupts. This warning can be suppressed by placing the directive SUPPRESS_NOP_AFTER_DINT_WARNING on the line before the instruction that triggered the warning.
- CPU40:
  
  For the MSP430X architecture (-v1), the assembler issues a warning whenever the last instruction in a segment part is a jump instruction. If you put data right after a jump inside the same segment part, you must take care to ensure that the data word right after the jump does not trigger CPU40. We recommend putting a nop after each jump that is followed by a data directive in the same segment part.
Hardware achitecture notes:
- The MSP430X architecture requires that a DINT or other instruction that disables interrupts must be followed by a NOP.
  
  When the -v1 option is given to the assembler, it will issue a warning if it detects an instruction that might disable interrupts unless it is followed by a NOP. If you are sure that the instruction in question can not disable interrupts, you can suppress the warning by placing the assembler directive SUPPRESS_NOP_AFTER_DINT_WARNING on the line just before the line that triggers the warning.
- The MSP430X architecture requires that the GIE bit in the status register SR is not set by one instruction and then cleared by the next instruction, for example by the code sequence EINT; DINT;.
  
  When the -v1 option is given to the assembler, it will issue a warning if it detects an instruction sequence that might do this. If you are sure that the instructions in question can never set and then immediately clear the GIE bit, you can suppress the warning by placing the assembler directive SUPPRESS_THIS_GIE_NOP_WARNING on the line just before the line that triggers the warning.
- The MSP430X architecture requires that interrupt flags must not be reset by the instruction immediately before an EINT or other instruction that enables interrupts.
  
  When the -v1 option is given to the assembler, it will issue a warning if it detects an instruction that might enable interrupts, unless it is preceded by a NOP. If you are sure that the instruction before the EINT can never reset any interrupt flags, you can suppress the warning by placing the assembler directive SUPPRESS_NOP_BEFORE_EINT_WARNING on the line just before the line that triggers the warning.

Release history

Version 6.40.1

New features

New mode control directives CODE, DATA, DATA8, DATA16, DATA24, DATA32, and DATA64 specify the type subsequence instructions. This helps the debugger to disassemble the instructions properly.
New command line options --data_model, --code_model, and --ropi. The command line options set a number of preprocessor symbols which can be used by assembly modules.

The preprocessor symbols USE_LARGE_CODE_MODEL and REGISTER_MODEL_REG20 should no longer be used.

Program corrections

EW25751: The assembler might produce an internal error when resolving the size of instructions/directives that depend on the offset in the segment.

Version 6.30.1

A new function directive has been added, CALL_GRAPH_ROOT caller, category.

New call frame information directives have been added for stack usage analysis:

CFI FUNCALL { caller } callee
CFI TAILCALL { caller } callee
CFI INDIRECTCALL { caller }
CFI NOCALLS { caller }

Version 6.20.1

A new option --no_ubrof_messages that can be used to minimize the size of your application object file by excluding messages from the UBROF files.
Both the compiler and the assembler now support comparing __CORE__ with either __430__/__430X__ and __430_CORE__/__430X_CORE__, to allow code to be shared between C/C++ and assembler.
EW23191: Text labels and comments in libraries that are built from assembler source code can now be hidden if the option --no_ubrof_messages is used.

Version 6.10.1

EW24608: The instruction movx with symbolic destination mode no longer gets the wrong address.

5.60.1 - 2013-09-13

None.

5.52.1 - 2013-05-13

None.

5.51.5 - 2013-01-17

The assembler now detects and issues a warning when a NOP instruction is needed between two instructions which might enable and disable interrupts, respectively, as required by the architecture on devices based on the MSP430X core.

5.51.3 - 2012-11-27

The assembler now detects and issues a warning when a NOP instruction is needed between an EINT and a DINT instruction as required by the architecture on devices based on the CPUxv2 core.

5.50.1 - 2012-06-29

EW22728: If an include directive uses a symbol that is inside a skipped portion of a conditional preprocessor directive, that include directive is no longer parsed for validity.

5.40.1 - 2011-11-24

The IAR Assembler Reference Guide has been updated.

5.30.1 - 2011-06-30

EW22303: When using the instruction MOVX &abs, X(Ry) with a negative value on X, the instruction is now correctly generated by the assembler.

5.20.1 - 2010-12-01

None.

5.10.1 - 2010-04-12

None.

4.21.6

EW21259, EW21260: When using symbolic mode with a PC offset of 0xFFFE, the assembler calculated the wrong PC offset. This has been corrected.

4.21.2 2009-09-01

None.

4.11B 2008-07-10

None.

4.10A 2007-09-27

None.

3.42A 2006-12-07

An error message is issued if an instruction with immediate source operand is found in combination with the rpt instruction.

3.41A 2006-04-13

None.

3.40A 2005-12-19

Program corrections

EW17566: The check of max segment size was done before assembler optimization. This could lead to the error Error[66]: Segment too long (max is ffff) even when the segment was not to large.
EW17059: The default name of an object file or a list file generated from a source file that has a name containing several period characters "." is now generated correctly.

New features

A new option -v has been added to include support for the MSP430X architecture. See User guide corrections for more information.
A new assembler directive sfrl has been added. sfrl can be used to define SFR labels that require 4 byte accesses.
A new predefined symbol __CORE__ has been added in the assembler. It reflects the -v option and can be used to determin which MSP430 architecture the code was built for. See User guide corrections for more information.

3.30A 2005-04-18

None.

3.21A 2004-10-20

The option -v[0|1] has been removed.

3.20A 2004-06-18

Program corrections

None.

New features

A new option -v has been added to include support for 128-Kbyte devices. See User guide corrections for more information.
A new data allocation directive WD16 has been added to make it possible to define a constant that points to the address range 0x10000 - 0x1FFFF. See User guide corrections for more information.

3.10A 2004-03-04

None.

2.21B 2003-11-14

None.

2.21A 2003-10-17

EW13891: An internal error related to assembler macros has been corrected.
EW14310: An internal error could occur when debug information was generated, and assembler macros where used.

2.20A 2003-05-23

None.

2.10A 2003-02-28

Program corrections

None.

New features

The assembler now generates a warning if an instruction has been placed on an odd address because of a preceding declaration or allocation of an odd number of bytes of data.

1.26B 2002-10-11

EW11655: The assembler could not correctly handle sequential REPT directives inside a REPT directive.
EW11675: When the .double directive was used to define a 48-bit floating point value in Texas Instrument format, the assembler allocated 3 words but made the calculations with 4. This caused all labels following this declaration to be placed on wrong addresses. The problem has been corrected so that 4 words are allocated.

1.26A 2002-02-26

None.

1.25A 2001-11-09

None.

1.24A 2001-04-06

The option -re (Generate source file embedded in the object file),
is now available in the IAR Embedded Workbench.

1.23A 2000-10-13

The IAR Assembler now supports access to the constant generator by using the various addressing modes and the registers R2 and R3.
A0006: To compare a string with a register is not possible, the assembler
should not generate an internal error, example: CMP #'HS',R1.
A1010A: Using SET or EQU to nickname a register is not possible, the assembler should not generate an internal error.

1.22E 2000-06-26

A0005: It was not possible to use a space after the ending quotation mark when using DB to create a string without a trailing zero. Everything following the space was ignored.
A0004: The following code with LABEL1 located in an absolute segment:
```
ASEG 0x200
LABEL1 DS 2
RSEG CODE
MOV 0200h(R5),LABEL1
```
generated the following error:
"Error [400]: Absolute operand is not possible here"
AFE0103: Undefined symbols in IF/ENDIF macro statements sometimes caused internal errors after the appropriate error message had been displayed. This has been corrected.

1.22A 1999-11-25

AFE0098: Alignments are now calculated correctly when preceded by a non-fixed instruction.

1.20A 1999-01-25

A0001: An error occured when a suffix (e.g. .B) was used as a symbol (SET, EQU and DEFINE). This has been corrected.
A0002: An internal error produced when comments were placed on the same line as assembler statements. This has been corrected.
A0003: Operators of equal precedence are evaluated from right to left instead of left to right. This has been corrected.

IAR Information Center for MSP430

Important information

Deprecated features

New features

Known Problems

Program Corrections

User guide corrections

Miscellaneous

Release history

Version 6.40.1

New features

Program corrections

Version 6.30.1

Version 6.20.1

Version 6.10.1

5.60.1 - 2013-09-13

5.52.1 - 2013-05-13

5.51.5 - 2013-01-17

5.51.3 - 2012-11-27

5.50.1 - 2012-06-29

5.40.1 - 2011-11-24

5.30.1 - 2011-06-30

5.20.1 - 2010-12-01

5.10.1 - 2010-04-12

4.21.6

4.21.2 2009-09-01

4.11B 2008-07-10

4.10A 2007-09-27

3.42A 2006-12-07

3.41A 2006-04-13

3.40A 2005-12-19

3.30A 2005-04-18

3.21A 2004-10-20

3.20A 2004-06-18

3.10A 2004-03-04

2.21B 2003-11-14

2.21A 2003-10-17

2.20A 2003-05-23

2.10A 2003-02-28

1.26B 2002-10-11

1.26A 2002-02-26

1.25A 2001-11-09

1.24A 2001-04-06

1.23A 2000-10-13

1.22E 2000-06-26

1.22A 1999-11-25

1.20A 1999-01-25