IAR Information Center for Arm

To connect with SWD to a device using DPv3 (for example most Cortex-M55 and Cortex-M85 devices), using an I-jet debug probe, the command line option --jet_emu_param=JtagDormant=1 must be added on the Project>Options>Debugger>Extra Options page.
To enable PTM Trace select On-Chip (ETB/MTB) in Project>Options>Debugger>I-jet>Trace

If PTM could not be automatically detected, add the option --jet_sigprobe_opt=trace(ETB,baseptm=<base PTM address + access port number>, baseetb=<base ETB address + access port number>) in Project>Options>Debugger>Extra Options

Example where port number is 1, Base PTM address is 0x8009D000 and base ETB address is 0x80001000
--jet_sigprobe_opt=trace(ETB,baseptm=0x8009D001,baseetb=0x80001001)
Information about I-jet firmware versions.
Unlock utilities for STM32 devices are provided as C-SPY macros found in the Macro Quicklaunch window.
To trace a core with ETM Trace other than core 0 in a multicore SMP system, add the option
--trace_from_core=<core number> in Project>Options>Debugger>Extra Options.

For Xilinx Zynq 7000 devices also add the option --macro_param trace_core=<core number> in Project>Options>Debugger>Extra Options.
JTAGjet and JTAGjet-Trace are no longer supported since EWARM 9.40.1. JTAGjet-Trace support has been deprecated since EWARM 8.40.1.

See New features for the IAR C-SPY Debugger.

Arm Embedded Trace Router (ETR) trace setup

For devices that support the ETR trace feature (for example Renesas RZ/N1), the trace buffer memory layout can be specified on the Extra Options page in the Debugger category of the Project>Options dialog box.

The available parameters are:
- --macro_param etrram=0x040A0000: The start of the RAM area to use for trace storage (for example 0x040A0000). If not specified, ETB trace will be used instead of ETR.
- --macro_param etrsize=0x60000: The size of the RAM area to use for trace storage (for example 0x60000).
- --macro_param etrport=1: The access port that will be used to access the ETR RAM. If not specified and if ETR is enabled, the port that is used to access the core will be used.