IAR Information Center for Arm

• Important information
• New features
• Known problems
• Program corrections
• User guide corrections
• Miscellaneous
• Release history

Important information

• The assembler and Warning[25]
  The assembler is now issuing Warning[25] for a deprecated assembler construction. The deprecated assembler source construction looks like this:

      PUBWEAK NMI_Handler
      SECTION .text:CODE:REORDER(1)
      NMI_Handler

  To avoid the warning, add :NOROOT to the SECTION statement:

      PUBWEAK NMI_Handler
      SECTION .text:CODE:REORDER:NOROOT(1)
      NMI_Handler

  Example of Warning[25]:
  ...\vec.s(172) : Warning[25]: Label 'NMI_Handler' is defined pubweak in a section implicitly declared root

• Deprecated features

  • XScale coprocessor instructions
    The IAR Assembler for ARM 7.40 does not recognize the XScale coprocessor instructions MIA, MIAPH, MIA{B,T}{B,T}, MAR, and MRA.

New features

• None

Known problems

• [EWARM-12211, TPB-3859]

  The assembler preprocessor does not ignore unrecognized directives in skipped preprocessor groups.
  For example:

          #if 0
          #unrecognized // Error[18]: No such pre-processor command: 'unrecognized'
          #endif

• [EWARM-10206, TPB-3665] Using a recursive macro call as an argument to a macro causes an internal error in the assembler. Example:
  #define A(a) a
  #define B(b) b
  #define C(c) c
  A(B(C(C( x )))

  Workaround: Clone the macro that is invoked recursively, removing the recursion in the invocation. In this example, do:
  #define A(a) a
  #define B(b) b
  #define C(c) c
  #define D(c) c
  A(B(C(D( x ))))

• [EWARM-8873, TPB-3526] If a defined function-macro is called without a start parenthesis the error Error[26]: '(' expected is issued followed by an internal error.

  Workaround: Add the parameters to the macro.

• [EWARM-4490, EW23889] Assembler file listing containing initializers for a data object that has a type that uses __packed or #pragma pack, is incorrect.

• [EWARM-3683, TPB-2031, EW21575] When the C-style preprocessor performs macro expansion, any identifier that matches a base mnemnonic will also match conditional variants, so for example "#define B 42" will effectively define also "BNE" and "BGE" (etc) as 42.

• [EWARM-3407, EW20356] Assembler directives may not appear within an IT-block (the consitional instructions following an IT-instruction). The limitation does not apply to C-style preprocessor directives, which are processed before any assembler instruction has been parsed. If an assembler directive is found within an IT-block, the block is considered to end and IASMARM will report error #429: 'IT-block contains too few instructions'. A possible workaround is to use a corresponding C-style preprocessor directive instead, if possible (for example, use '#if' instead of 'IF').

Program corrections

• None

User guide corrections

• The command line option --no_dwarf4 is not described in the IAR Assembler User Guide.
  
  Syntax: --no_dwarf4
  Description: Use this option to suppress generation of DWARF 4 debug information. This will lead to a degraded debugging experience, but might allow loading in a debugger that a does not support DWARF 4.

Miscellaneous

• None.

Release history

V9.50 2023-11-28

Program corrections

• None

New features

• None

V9.40 2023-05-24

Program corrections

• None

New features

• None

V9.32 2022-12-13

Program corrections

• [EWARM-10574] The assembler CFI directives truncate any expressions for integer constants to 32 bits—in particular, this is a problem for CFI RESOURCE expression and CFI RESOURCE LITERAL(expression).

• [EWARM-10417] For Armv6-M cores, the assembler incorrectly accepts MSPLIM or PSPLIM as the special register name in MSR/MRS instructions. These registers were first introduced in Armv8-M.

New features

• None

V9.30 2022-06-02

Program corrections

• [EWARM-10075] The assembler produces an internal error if a floating-point constant has f, F, l, or L as a suffix.

New features

• [AFE1] The assembler now has two options for producing dependency lists: -y {file|path} and -Y[path]. The "one rule" make format is used.

• The inline assembler operand constraint "digit" has been added.

V9.20 2021-11-02

Program corrections

• [EWARM-8847] In 64-bit mode, the Arm disassembler sometimes displays and incorrectly masks literals for logical instructions.

New features

• None

V9.10 2021-02-19

Program corrections

• In EWARM 9.10.2
  [EWARM-8753, TPB-3517] The AFE1 assembler constant folds the operators >> and << erroneously if the shift amount is larger than 31 and the expressions size is 64-bit. For example 0x8000000000 >> 32 will get an erroneous result.

• In EWARM 9.10.2
  [EWARM-8741] The PSTATE field name specified in the immediate variant of the MSR instruction should not be case sensitive. Currently, the name is only recognized if the first letter is uppercase. Specifying an initial lowercase letter will result in an error.

• In EWARM 9.10.2
  [EWARM-8712] The message Error[406]: Bad data alignment is issued when a label in THUMB mode is used in an ADR.N instruction. The message can be misleading, because the problem is with the label in THUMB mode, which sets the low bit.

  The correct error message is: Error[559]: Bad data alignment, address of THUMB label is odd.

• [EWARM-6775, TPB-3228] A conditional directive following a comment placed in the first position on the line is parsed incorrectly.

New features

• None.

V8.50 2020-02-17

Program corrections

• In EWARM 8.50.4
  [EWARM-7571] A pseudo-instruction LDR Rt,=imm is implemented as MOV Rt,#imm when Rt is not the program counter register R15, and there is a valid instruction encoding for the value imm.

  The MOV instruction has unpredictable behavior when the destination is the stack pointer register, R13.

New features

• None.

V8.42 2020-01-17

Program corrections

• [EWARM-7097, TPB-3232] The version string reported by iasmarm --version does not end with a newline character.

• [EWARM-7076] The assembler reports an internal error for Thumb2 when the following is true: an instruction LDR <Rt>,=<expr> is used, <Rt> is not PC, and the value of <expr> is known and can be represented as a (possibly negated) 12-bit modified Thumb immediate constant.

New features

• None.

V8.40 2019-05-24

Program corrections

• In EWARM 8.40.2:
  [EWARM-6765] It is not possible to use the 2-operand variants of the ADDS instruction.
  See also EWARM-6939

• [EWARM-6445, TPB-3030] The assembler issues an internal error if a FUNCALL caller symbol isn't used in the rest of the assembler source.

New features

• None.

V8.32 2018-10-12

Program corrections

• None.

New features

• None.

V8.30 2018-06-15

Program corrections

• [EWARM-6210, TPB-2956] The compiler will crash with an out of memory error when compiling inline assembler statements containing two consecutive % characters.

New features

• None.

V8.22 2018-01-22

Program corrections

• None

New features

• None

V8.20 2017-10-16

Program corrections

• [EWARM-5816, EW26743] In rare cases when the source file has a long name, the assembler may generate an internal error when writing warning or error messages to a list file.

• [EWARM-5550, EW26294] A misleading warning "Set section alignment the same(2) or larger" was
  issued for the following (unrelated) section when there are LDR
  pseudo-instructions that adds literal pool data in an unaligned section
  without an LTORG directive.
  A new warning has been introduced, "Data in literal pool may be
  misaligned after linking", which is issued for any LDR
  pseudo-instruction within a section that is not properly aligned.

New features

• None

V8.11 2017-04-11

Program corrections

• In EWARM 8.11.2:
  When the assembler reads an extended command line (.xcl) file, backslash characters inside quoted token parts are not interpreted correctly. In particular, this makes it impossible to define macros (-D) containing quoted strings, using the Defined symbols field on the Assembler>Preprocessor page in the Project>Options dialog box in the IDE.
  [EW26533]

• In EWARM 8.11.3:
  Invalid constraints in the assembler interface part of an inline assembler statement can trigger an internal error in the compiler.
  [EW26613]

New features

• None.

V8.10 2017-03-10

Program corrections

• None.

New features

• None.

V7.80 2016-10-17

Program corrections

• None.

New features

• None.

V7.70 2016-06-17

Program corrections

• None.

New features

• None.

V7.60 2015-03-31

Program corrections

• The correction for EW25467 is correct for instructions like LDM/LDMIA/LDMFD and STM/STMIA/STMEA, but it is incorrect for LDMDB/LDMEA and STMDB/STMFD.
  [EW25906]

• In EWARM 7.60.2:
  IASMARM reported errors due to ARM Cortex-M3 errata 602117 also for other Cortex-M devices.
  [EW26036]

New features

• None.

V7.50 2015-11-10

Program corrections

• None.

New features

• None.

V7.40 2015-02-19

Program corrections

• An internal error message is issued for non absolute sections defined with lower alignment than what its content needs.
  [EW25168, EW25204]

• In EWARM 7.40.5:
  The Thumb-2 encoding for LDM <Rn>!,<registers> is unpredictable when only a single register is loaded. However, according to the ARM reference manuals, the encoding should not be used. Instead the instruction should be assembled into a corresponding LDR instruction.
  [EW25467]

New features

• None.

V7.30 2014-09-24

Program corrections

• The assembler might terminate unexpectedly if an EQU instruction is used for defining a symbol declared as PUBWEAK.
  [EW24946]

• In EWARM 7.30.3:
  The assembler terminates unexpectedly if a symbol argument to a C preprocessor macro is a reference to an assembler macro (either directly or by taking the uppercase version of it).
  [EW24985]

New features

• None.

V7.20 2014-05-19

Program corrections

• The assembler no longer reports "expression out of range" for a BFI instruction with a 32-bit width starting from bit 0.
  [EW24691]

• In EWARM 7.20.2:
  The assembler now generates the VFNMA and VFNMS instructions according to ARM DDI 0403E.a
  [EW24745]

New features

• None.

V7.10 2014-02-21

Program corrections

• Backward references could be generated for LDR <Rt>,=<expr> in THUMB mode, which results in a bad offset because only forward references are supported.
  [EW24437]

• In EWARM 7.10.3:
  An internal error will occur when generating code for Thumb-1 for source code that matches a bitwise left rotate if the rotation count is unknown and register R12 is allocated to hold the count for a ROR instruction (rotate right).
  [EW24582]

New features

• None.

V6.70 2013-10-29

Program corrections

• In EWARM 6.70.2:
  Generation of a literal pool, for example by LTORG, does not reliably switch to DATA mode before the generated data table. This can lead to symptoms such as the linker error Lp029: instruction validation failure (since data is interpreted as code).
  The obvious workaround is to add a DATA directive immediatelly before the LTORG directive.
  [EW24145]

New features

• None.

V6.60 2013-06-27

Program corrections

• The assembler now allows a function-like macro in an include directive.
  [EW23883]

New features

• None.

V6.50 2012-11-10

Program corrections

• The preprocessor in the assembler changed a used symbol in a macro to become absolute when the macro was used for defining a label. This has been corrected.
  [EW23446]

• The LTORG directive now restores Thumb mode correctly after inserting a literal pool.
  [EW23489]

• In EWARM 6.50.2:
  The instructions MCR and MRC now allow # before operation code operands also in Thumb mode.
  [EW23559]

• In EWARM 6.50.3:
  A condition was silently ignored for some unconditional instructions (CPS, SRS, DMB, DSB, ISB, PLI and SETEND). An error is now issued.
  [EW23621]

New features

• None.

V6.40 2012-06-05

Program corrections

• The assembler now issues an error for a CPSID or CPSIE instruction attempting to access the flag f in the architecture ARMv6-M (Cortex-M0).
  [EW22873]

• An include directive using a symbol, which is inside a skipped portion of a conditional preprocessor directive, is no longer parsed for validity.
  [EW22993]

• In EWARM 6.40.4:
  The assembler no longer dereferences a null pointer when verifying an IT block containing a PUBLIC directive.
  [EW23455]

New features

• None.

V6.30 2011-10-22

Program corrections

• Relocation of LDRD (literal) will cause linking to fail if the reference is backwards. To address this issue, an unsolved literal is no longer allowed unless the assembler can determine it to be a forward reference.
  [EW22726]

New features

• None.

V6.21 2011-07-05

Program corrections

• The assembler now accepts pre-UAL syntax (for example MOV<c>S) also for BICS, ORRS and ANDS.
  [EW22459]

• In EWARM 6.21.4:
  The instructions SMLAWB, SMLAWT, SMULBB, SMULBT, SMULTB, and SMULTT are no longer available when assembling for Cortex-M3 since they require the media extensions of Cortex-M4.
  [EW22553]

New features

• None.

V6.20 2011-04-29

Program corrections

• The asembler can now parse the keywords ELSE, ELSIF, and ENDIF even if a C/C++ comment follows without separation.
  [EW22296]

• In EWARM 6.20.2:
  The assembler will no longer issue an internal error after reporting "expression out of range" for instructions of the form LSR{S} ,,#0".
  [EW22406]

New features

• None.

V6.10 2010-11-04

Program corrections

• The use of an EQUated symbol no longer generates an internal error.
  [EW21616]

• The assembler now generates an error whenever it can't continue generating ELF after previous errors.
  [EW21760]

• Assembler for ARMv6-M no longer accepts Thumb-2 variants of immediate bitwise logical instructions (ORR, AND, BIC, EOR) or comparisons (CMP, CMN, TST, TEQ).
  [EW21980]

New features

• None.

V5.50 2010-04-21

Program corrections

• The SRS instruction syntax with explicit SP as first operand is now recognized.
  [EW21571]

• The immediate variants of Thumb-2 instructions CMN, CMP, TEQ, and TST are no longer accepted for non-Thumb-2 architectures.
  [EW21644]

• ARM1136 is considered ARMv6K. This is correct for core revisions r1p0 and later.
  [EW21653]

New features

• None.

V5.41 2009-12-14

• In EWARM 5.41.2:
  LDR with SP as the destination register is no longer reported as an unpredictable instruction.
  [EW21576]

V5.40 2009-07-10

• The MOVT instruction has been corrected to move the bottom halfword of the immediate value into the top halfword of the destination of the destination register. Previously the top halfword of the immediate value was used.
  [EW20852]

• The assembler now reports an illegal register error instead of the warning unpredictable register combination when SP or PC is in the register list of an STM instruction in Thumb mode. Similarly for SP and the LDM instruction.
  [EW20854]

• In EWARM 5.40.4:
  The implicit Thumb mode for Cortex-M when no explicit THUMB directive is used, now marks labels as odd.
  [EW20359,EW21173]

• In EWARM 5.40.4:
  Assembly of conditional BLX in Thumb mode no longer results in internal error.
  [EW21182]

• In EWARM 5.40.4:
  The SVC instruction is now available when assembling for Cortex-M0.
  [EW21213]

• In EWARM 5.40.4:
  In the CODE16 mode an unconditional branch could become a BEQ with an 8-bit offset, which has no encoding for AL (the always condition). The correct 11-bit offset encoding is now used for unconditional branches.
  [EW21257]

V5.30 2009-01-23

• The handling of branch length corner cases for Thumb2 ISA has been improved. The reduced instruction size is now taken into account when attempting to select a smaller branch. If an instruction between a branch and its target label is shrunk, a wide branch might still be generated in corner cases where a narrow branch could have been used.
  [EW20357]

• Incorrect warning is no longer emitted.
  [EW20358]

• The SMC instruction is now available with arm1176(f)jz cores.
  [EW20388]

• The assembler can now parse a multibyte comment inside a macro definition.
  [EW20510]

V5.20 2008-06-24

• Invalid instructions could generate internal errors.
  [EW19411, EW19733]

• The assembler can now handle a local label definition followed by a segment definition that uses the same name.
  [EW19474]

• Some needed system registers have been added in v6M mode.
  [EW19813]

V5.11 2007-12-11

• The assembler now uses absolute paths to all source files referred to in the debug information in the object file.
  [EW18901]

• The assembler now interprets the parameter to the options -L, -O, and -I as a directory path only. The previous prefix behavior has been removed.
  [EW18903]

• When a CPU core with a VFP coprocessor is selected, an error is no longer generated if you try to disable it with --vfp=none.
  [EW19073]

• The assembler can now handle a local label definition followed by a segment definition that uses the same name.
  [EW19474]

• Relocatable expressions no longer give internal errors.
  [EW19580]

• The assembler no longer generates an internal error for certain PC-relative expressions.
  [EW19676]

V5.10 2007-05-25

• If you specify the assembler option -j, the assembler will recognize the instruction syntax used by the TASM assembler from Advanced RISC Machines Ltd. In version 4.40A, the instruction mnemonics CMPS, CMNS, TEQS, and TSTS were accidentally removed, but have been reintroduced in this version.
  [EW18338]

V4.41A 2006-12-08

• When using the assembler option -j, the assembler will recognize the instruction syntax used by the TASM assembler from Advanced RISC Machines Ltd. In version 4.40A, the instruction mnemonics CMPS, CMNS, TEQS, and TSTS were accidentally removed but have been reintroduced in this version.
  [EW18338]

V4.40A 2006-06-03

• The instruction "SRSIB #" was incorrectly assembled and generated an incorrect opcode.
  [EW17795]

• Some 16-bit Thumb instructions incorrectly accepted the writeback modifier, but ignored it during code generation. The writeback modified is no longer accepted in these cases.
  [EW17829]

• Using the command line option --cpu to specify any of the cores ARM1136JF, ARM1136JF-S, ARM1176JF, or ARM1176JF-S caused an internal error in the assembler.
  [EW17838]

• If the Thumb mode BLX instruction was used to call an ARM function located in the same code segment, the branch offset could be incorrectly calculated causing an illegal instruction to be generated.
  [EW17959]

• When assembler instructions were used incorrectly (wrong syntax, branch offset too large, etc.), an error message was issued. However, in some cases, after issuing the correct error message, the assembler stopped with an internal error message. Examples are:
  - Thumb mode BLX, where branch offset is too large
  - ARM mode coprocessor instructions with a bad syntax
  [EW17967]

• The --fpu command line option is used to specify the FPU for the device. If an illegal value was given, the assembler did not give an error message. Instead, it was handled as if no FPU was available. An error message is now given if an illegal value is given to the --fpu option.
  [EW18009]

• Selecting a cpu or architecture with the command line option --cpu will result in preprocessor symbols being defined by the assembler. However, the preprocessor symbols were not correctly set for all values of --cpu in the previous version. Symbol __ARM6__ was incorrectly set for CPUs from the ARM9, ARM10, and XScale cpu families, and if architecture "5TE" was specified.
  In addition, besides recognizing new ARM6T2 and ARM7M cpu:s, the correct fpu will automatically be selected if specifying a cpu with an fpu.
  [EW18016]

• The normal format for adding/subtracting an immediate value using the ADD/SUB instructions is "ADD Rd, Rn, #value", where the value for most constants represents a positive value. The assembler also accepts the instruction with a negative immediate value. In this case, the instruction is silently converted, so that ADD of a negative value is replaced with a SUB of the corresponding positive value. This replacement was incorrect for ADD/SUB, when the constant is larger than 0xFF, i.e. when the instruction encoding requires an shift value to be encoded.
  [EW18043]

V4.31A 2006-02-03

• The CODE32 directive now aligns correctly.
  [EW17286]

• Instruction parsing could be incorrect for some instructions in special situations. If a conditional instruction was placed inside a macro, and the instruction was preceeded by a label, the condition code was not correctly handled.
  [EW17528]

• For data processing instructions where the source is an immediate value with a specified rotation count, and the destination register is a high register (R8 - R15), the generated opcode was incorrect. Example of an incorrectly handled instruction:
  ADD R9, R9, #63, 4
  [EW17659]

• The 3-operand data processing instructions (ADD etc) now fully accept the syntax
  <op> <Rd>, <Rn>, #<immediate>, <rotation>
  for all combinations of immediate and rotation values calculated either at assembly time or at link time.
  [EW17579]

• The CMP/CMN/TST/TEQ instructions did not support the syntax
  <op> <Rn>, #<imm>, <rot>
  [EW17660]

• The VFP instructions FSTM and FLDM are normally written with the addressing modes IA or DB. If used in situations where data is loaded or stored from/to a stack, the addressing mode names EA and FD must be supported as synonyms.
  [EW17661]

• The ARM mode MOV Rd, #imm instruction now accepts negative constants by automatically changing the MOV instuction to an MVN instruction. MVN can be changed into a MOV instruction correspondingly.
  [EW17666]

• The VFP instruction FSTMIAX generated the wrong opcode. The same opcode as FSTMIAD was generated.
  [EW17670]

• If the offset is negative in an instruction on the form
  LDC/STC{2} <coproc>, <CRd>, [<Rn>,#-]{!}
  the assembler earlier incorrectly generated the opcode for the corresponding instruction with a positive offset.
  [EW17679]

• If the PC-relative syntax for the FLDS instruction was used (FDLS Rd, label), and the label was located so that the offset was negative (label placed earlier than eight bytes after the instruction), the generated opcode for the instruction was incorrect.
  [EW17680]

V4.30A 2005-06-23

• Some illegal assembler instructions could cause an internal error instead of a syntax error.
  Example:

  MOV R0, @R1

  [EW16414]

• "Warning[401]: Base register in Register list" was sometimes given for ldm instructions that didn't have writeback.
  [EW16455]

V4.20A 2005-01-10

• FLDS, FLDD, FSTS and FSTD can now have a relocatable offset. This is needed when accessing constants from VFP code.
  [EW15641,EW15998]

• An error that terminated the assembler unexpectedly if it encountered identifiers with more than 255 characters has been corrected. Now using such identifiers are reported as an error.
  [EW16099]

• BLX in ARM mode to a local thumb label could be incorrectly assembled.
  [EW16207]

V4.11A 2004-06-14

• The preprocessor couldn't quite handle a macro parameter that invoced another parameterized macro.
  [EW15241]
• Two or more tabs preceeding SMULxy, SMULWx SMLAxy, SMLAWx or SMLALxy could cause the assembler to fail.
  [EW15398]
• BLX in ARM mode to an extern Thumb label could be incorrectly assembled.
  [EW15484]
• The assembler gave internal error for the VFP instructions:

      FLDD d0,[r0]
      FLDS s0,[r0]
  

  [EW15998]

V4.10B 2004-03-09

• ARM VFP vector floating point coprocessor instructions are supported by the assembler. A new option, --fpu is available to select between different floating point alternatives.

V4.10A 2004-02-21

• Data definition directives immediately followed by a comment character gave a syntax error.
  

      DCD 5; this fails
      DCD 5 ; this works
  

  [EW13456]
• A forward reference of a label with the same name as a segment defined later gave an internal error. For example:
  

      rseg yyy
      dc32 xxx
  
      rseg xxx
      xxx:
      end
  

  [EW14442]
• The assembler calculated offsets between labels in different noroot segments incorrectly.
  [EW14476]
• The assembler handled SWI-instructions with a 24-bit operand as 'out of range'.
  [EW14785]
• Instructions of the form

      label mnemonic
  

  generated wrong code if the label contained any of the character sequences EQ, NE, CS, ... (conditional instruction keywords).
  [EW14855]

V3.40B-P1 2003-10-06

• The assembler previously aborted with an internal error when an excessive number of EQUs were present in the source code.
  [EW14351]

V3.40A 2003-07-03

• Compiler assembly output in interwork mode could fail to assemble.
  [EW13604]
• An assembler syntax error was generated when R15/PC was used as the <Rd> operand of the MRC instruction.
  [EW14087]

V3.30A 2003-02-17

• Assembler syntax coloring did not work.
  [EW12809]
• The code cmp r0,#-1 in ARM mode gave a range error.
  [EW12329]
• Missing error message for conflicting operands in mul r0,r0.
  [EW13361]

V3.21A 2002-09-27

• The Thumb mnemonics LDRSH and LDRSB are now recognized.
  [EW12311]

V3.20A 2002-06-18

• The ARM instruction set version 5TE is now supported.
  To use it add command-line option --cpu {target core or architecture name}.

• Byte order can now be specified with the command line option
  --endian {little | l | big | b}

V3.11A 2001-12-04

• None.

V3.10A 2001-10-04

• None.

V2.10D 2001-06-29

• The assembler crashed on the use of SYMBOL directives as generated by the compiler. The SYMBOL directive is used to handle C++ scoped names. It caused a problem when assembling an assembler file generated by the compiler.
  [EW10297]

V2.10A 2001-02-21

• Support for big-endian byte order implemented, option -e.

V1.30A 2000-09-08

• The XLINK option -O can be used to produce multiple output files. Syntax:
  

      -Oformat[,variant][=filename]
  

  The option is described in the XLINK documentation.

V1.20B 2000-06-14

• Initialization problem in aarm.dll corrected.

V1.20A 2000-05-30

• None

V1.10B 2000-01-14

• ADR in Thumb mode was incorrect, and has now been corrected.
• LDR alignment checking has been modified.

V1.10A 1999-12-30

• First release.