Published October 14, 2019.
Highlights
Performance optimizations
This release includes a number of optimizations for execution speed
Support for the .insn directive.
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This feature adds the possibility to generate instructions on all RISC-V instruction formats and can be used to generate custom instructions not directly supported by the assembler.
Initial support for debug access trough DAP makes
it possible to debug a RISC-V core that is connected through an Arm Debug Access Port
This release adds basic support for cJTAG debug connections
Program corrections (1.11.2)
This service pack includes a correction of the debugger where the state of a CPU loaded on an Arty 100T board could be incorrectly detected as in reset.
Device support
This release adds support for the following cores
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Andes N22
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MicroSemi Mi-V RV32 RISC-V softcores
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Syntacore SCR1
Download installer for Windows (
250.5 MB)
| Languages: | English, Japanese |
A valid Support and Update Agreement is required for this download.
How to Install:
Execute the downloaded file.
The installer should not be installed on top of an existing EWRISCV installation, it is recommended to be installed as a new instance.